Alif Semiconductor /AE512F80F5582AS_CM55_HP_View /OSPI0 /OSPI_RISR

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Interpret as OSPI_RISR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)TXEIR 0 (Val_0x0)TXOIR 0 (Val_0x0)RXUIR 0 (Val_0x0)RXOIR 0 (Val_0x0)RXFIR 0 (Val_0x0)TXUIR

TXEIR=Val_0x0, RXFIR=Val_0x0, RXOIR=Val_0x0, RXUIR=Val_0x0, TXOIR=Val_0x0, TXUIR=Val_0x0

Description

OSPI Raw Interrupt Status Register

Fields

TXEIR

Transmit FIFO Empty Raw Interrupt Status.

0 (Val_0x0): Transmit FIFO Empty interrupt is not active prior masking.

1 (Val_0x1): Transmit FIFO Empty interrupt is active prior to masking.

TXOIR

Transmit FIFO Overflow Raw Interrupt Status.

0 (Val_0x0): Transmit FIFO Overflow interrupt is not active prior masking.

1 (Val_0x1): Transmit FIFO Overflow interrupt is active prior to masking.

RXUIR

Receive FIFO Underflow Raw Interrupt Status.

0 (Val_0x0): Receive FIFO Underflow interrupt is not active prior masking.

1 (Val_0x1): Receive FIFO Underflow interrupt is active prior to masking.

RXOIR

Receive FIFO Overflow Raw Interrupt Status.

0 (Val_0x0): Receive FIFO Overflow interrupt is not active prior masking.

1 (Val_0x1): Receive FIFO Overflow interrupt is active prior to masking.

RXFIR

Receive FIFO Full Raw Interrupt Status.

0 (Val_0x0): Receive FIFO Full interrupt is not active prior masking.

1 (Val_0x1): Receive FIFO Full interrupt is active prior to masking.

TXUIR

Transmit FIFO Underflow Interrupt Raw Status

0 (Val_0x0): Transmit FIFO Underflow interrupt is not active prior masking

1 (Val_0x1): Transmit FIFO Underflow interrupt is active prior to masking

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